module comp (
    a, b, agb, aeb, alb
);
    parameter n = 1;
    input [n-1:0] a, b;
    output reg agb;
    output reg aeb;
    output reg alb;
    
    always @(a or b) begin
        agb = a>b;
        aeb = a==b;
        alb = a<b;
    end

endmodule